1. Field of the Invention
The present invention relates to a timing control circuit for an LCD and method thereof, and more particularly, to a timing control circuit with power-saving function for an LCD and method thereof.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating an LCD 100. The LCD 100 comprises a timing control circuit 110, a data driving circuit 120, a gate driving circuit 130, and a pixel area 140. The timing control circuit 110 receives frame data externally, and respectively controls the data driving circuit 120 and gate driving circuit 130 according to the received frame data. The data driving circuit 120 transmits image signals to the pixel area 140. The gate driving circuit 130 transmits gate driving signals to the pixel area 140 to enable corresponding liquid crystal particles of the pixel receiving gate driving signals to rotate according to the image signals. In this way, frames can be displayed. Additionally, the interface between the timing control circuit 110 and the external devices is a Low Voltage Differential Signal (LVDS) interface. The interface between the timing control circuit 110, data driving circuit 120, and gate driving circuit 130 is a Reduced Swing Differential Signal (RSDS) interface. The above two interfaces carry voltage when enabled, which consumes power.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating a valid pixel area of the pixel area 140. As shown in FIG. 2, the pixels of the pixel area 140 are not entirely displayed on the LCD because some pixels are covered by the edges of the LCD, which are invalid pixels. Those pixels that can be displayed on the LCD are valid pixels, which are defined by the vertical synchronous signal Vs and the horizontal synchronous signal Hs. Generally, the invalid pixels are called “porch,” as the area covered by the widths of A, B, C, and D in FIG. 2. In the prior art, the porch is sent with black frame data, so that the porch still expresses a black frame with the corresponding grey level data.
However, the RSDS and LVDS interfaces still need to be enabled to transmit a grey level for black color to the invalid pixels according to the prior art. Therefore, the transmission lines of the RSDS and LVDS interfaces have to carry voltages, because the RSDS and LVDS interfaces transmit data in a differential manner. Hence, the LVDS interface between the timing control circuit 110 and the external devices, the RSDS interface between the timing control circuit 110 and the data driving circuit 120, and the RSDS interface between the timing control circuit 110 and the data driving circuit 130 have to remain enabled. In this way, even though a user cannot watch the black frames of the porch, the RSDS interface between the timing control circuit 110 and the data driving circuit 120, and the RSDS interface between the timing control circuit 110 and the data driving circuit 130 are still enabled, which wastes power.